PIC18F2520-I/ML【PDF 35/151 页】IC PIC MCU FLASH 16KX16 28QFN

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PIC16(L)F1782/3

DS41579C-page 302

Preliminary

2011-2012 Microchip Technology Inc.

26.6.7

I2C MASTER MODE RECEPTION

Master mode reception is enabled by programming the

Receive Enable bit, RCEN bit of the SSPCON2

The Baud Rate Generator begins counting and on each

rollover, the state of the SCL pin changes

(high-to-low/low-to-high) and data is shifted into the

SSPSR. After the falling edge of the eighth clock, the

receive enable flag is automatically cleared, the con-

tents of the SSPSR are loaded into the SSPBUF, the

BF flag bit is set, the SSPIF flag bit is set and the Baud

Rate Generator is suspended from counting, holding

SCL low. The MSSP is now in Idle state awaiting the

next command. When the buffer is read by the CPU,

the BF flag bit is automatically cleared. The user can

then send an Acknowledge bit at the end of reception

by setting the Acknowledge Sequence Enable, ACKEN

bit of the SSPCON2 register.

26.6.7.1

BF Status Flag

In receive operation, the BF bit is set when an address

or data byte is loaded into SSPBUF from SSPSR. It is

cleared when the SSPBUF register is read.

26.6.7.2

SSPOV Status Flag

In receive operation, the SSPOV bit is set when 8 bits

are received into the SSPSR and the BF flag bit is

already set from a previous reception.

26.6.7.3

WCOL Status Flag

If the user writes the SSPBUF when a receive is

already in progress (i.e., SSPSR is still shifting in a data

byte), the WCOL bit is set and the contents of the buffer

are unchanged (the write does not occur).

26.6.7.4

Typical Receive Sequence:

The user generates a Start condition by setting

the SEN bit of the SSPCON2 register.

SSPIF is set by hardware on completion of the

Start.

SSPIF is cleared by software.

User writes SSPBUF with the slave address to

transmit and the R/W bit set.

Address is shifted out the SDA pin until all 8 bits

are transmitted. Transmission begins as soon

as SSPBUF is written to.

The MSSP module shifts in the ACK bit from the

slave device and writes its value into the

ACKSTAT bit of the SSPCON2 register.

The MSSP module generates an interrupt at the

end of the ninth clock cycle by setting the SSPIF

bit.

User sets the RCEN bit of the SSPCON2 register

and the master clocks in a byte from the slave.

After the 8th falling edge of SCL, SSPIF and BF

are set.

10. Master clears SSPIF and reads the received

byte from SSPUF, clears BF.

11. Master sets ACK value sent to slave in ACKDT

bit of the SSPCON2 register and initiates the

ACK by setting the ACKEN bit.

12. Masters ACK is clocked out to the slave and

SSPIF is set.

13. User clears SSPIF.

14. Steps 8-13 are repeated for each received byte

from the slave.

15. Master sends a not ACK or Stop to end

communication.

Note:

The MSSP module must be in an Idle

state before the RCEN bit is set or the

RCEN bit will be disregarded.

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